Illegal assignment: Cannot assign an unpacked type to a packed type

In SystemVerilog I wrote:

module mult32x32_arith ( input logic clk, // Clock input logic reset, // Reset output logic [63:0] product // Miltiplication product ); logic left_decoder, right_decoder, product_FF[63:0]={64{1'b0}}; always_ff @(posedge clk, posedge reset) begin if (reset==1'b1)begin product <= product_FF; end else begin end end 

But, I'm getting errors on this line:

product <= product_FF; 

It says:

Error: mult32x32_arith.sv(19): Illegal assignment to type 'reg[63:0]' from type 'reg $[63:0]': Cannot assign an unpacked type to a packed type.

But, I don't understand what the problem is.

0

2 Answers

You declared product as packed and product_FF as unpacked. Refer to IEEE Std 1800-2017, section 7.4 Packed and unpacked arrays:

The term packed array is used to refer to the dimensions declared before the data identifier name. The term unpacked array is used to refer to the dimensions declared after the data identifier name

You need to declare them as the same data type. For example, to make them both packed, change:

logic left_decoder, right_decoder, product_FF[63:0]={64{1'b0}}; 

to:

logic left_decoder, right_decoder; logic [63:0] product_FF = {64{1'b0}}; 

There is an easier solution: bitstream cast - see Section 6.24.1 in the language specification

typedef logic[63:0] packed_64;

and then the assignment

product <= packed_64'(product_FF);

Maybe the typedef is unnecessary, haven't tested it.

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